This invention relates to processes for integrated circuit manufacturing, and in particular to processes for plasma etching of low dielectric constant dielectric layers and wafers made by the process.
Integrated circuits are becoming ever smaller, faster, and cheaper to produce. Accordingly, device geometries and minimum feature sizes are shrinking, and are currently commercially available down to 0.25 microns. In this size regime, the resistance and capacitance of interconnect lines providing electrical connection between devices plays an increasingly large role in determining speed and performance of the integrated circuit. As a result, in integrated circuit research and development, increasing attention has focused on reducing the resistance and capacitance of interconnect lines.
The distributed capacitance of a metal line running over or through a dielectric layer is proportional to the dielectric constant of the dielectric. Therefore, utilizing dielectrics having a low dielectric constant in integrated circuit processes, as the interlevel dielectric in multilevel metallization structures by way of example, is one important method of increasing speed and improving performance. One such dielectric with a low dielectric constant is a spin-on material known as HSQ, Hydrogen Silsesquioxane, which is utilized as a planarizing bottom layer in an interlevel dielectric stack, as illustrated in FIG. 1a. In this capacity, a contact or via etch must be performed through the HSQ and any other dielectric layers in the stack to provide an aperture for depositing a low resistance connection between metal layers. This contact or via etch process must be highly anisotropic in order to etch deep but narrow vias or contacts i.e., high aspect ratio vias or contacts. It must also have excellent selectivity with respect to the stopping material, which for most current applications is Ti or TiN, but may be Si, silicon nitride, or metals such as Al, Cu, or Ta, depending on the details of the process. Selectivity is required in order to allow overetch, so that the deepest contact/via is etched through without destroying the region beneath the shallowest contact/via. If the wafer surface is not exactly planar, there will always be contacts/vias of somewhat differing depths.
Standard contact/via etch processes have been developed having the requisite selectivity and anisotropy for interlevel dielectrics comprising oxides such as TEOS (tetraethylorthosilicate). One known contact/via dry etch method is performed in a high density plasma (HDP). Specialized etch machines have been developed for HDP etch such as the Applied Materials Centura 5300 or the Lam 9100. These high ion density machines operate in a lower pressure regime than standard plasma etch machines. The lowered pressures result in a more anisotropic etch, due to decreased ion collisions and scattering. The generally used etch gas for oxide etch comprises C2F6. The process selectivity of oxide to an underlying etch stop layer is generally achieved by allowing the formation of polymer, which is deposited in the contact/via during oxide etch but reacts away faster than it deposits. When the underlying layer is reached, the polymer deposits on the surface of non-oxygen containing layer faster than it volatilizes and causes etch stop.
However, when HSQ has been previously etched using C2F6 chemistry in an HDP reactor for a large wafer, however, etching would stop in some vias before reaching the etch stop layer and this would prevent effective HSQ etch, particularly when the HSQ layer is below a TEOS layer. Additionally, substantial etch non-uniformity has occurred from the center to the edge of the wafer. This has resulted in problems with xe2x80x9cpunch-throughxe2x80x9d of the etch stop layer, i.e., etching completely through the etch stop, on portions of the wafer. One factor believed to contribute to these effects is that the HSQ contains hydrogen and contains less oxygen than silicon dioxide. This is believed to promote increased polymer formation and deposition during HSQ etch as compared to SiO2 etch. Attempts by several research groups to solve these problems and thereby realize a useful TEOS/HSQ etch in an HDP reactor have until now been largely unsuccessful.
It is therefore an object of this invention to provide an improved wafer for integrated circuits and a manufacturing process in a high-density plasma reactor which can be utilized to etch high aspect ratio contacts or vias through dielectrics where the dielectric includes HSQ.
Another object of this invention is to provide a manufacturing process for etching HSQ in a high-density plasma reactor which does not evidence an etch-stop effect at a dielectric interface during HSQ etch.
Another object of this invention is to provide a manufacturing process for etching HSQ in a high-density plasma reactor which has high anisotropy.
Another object of this invention is to provide a manufacturing process for etching HSQ in a high-density plasma reactor which has high selectivity over underlying layers.
Another object of this invention is to provide a wafer and a manufacturing process therefor for etching HSQ in a high-density plasma reactor which has improved across-the-wafer uniformity.